Metal-insulator phase transition flip-flop

ABSTRACT

A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device.

CROSS-REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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BACKGROUND

Modern computers and related processing systems typically include aprocessor and some form of memory. The processor is generallyresponsible for performing the various computational tasks of thecomputer while the memory stores data that is used in and generated bythe computational tasks. The architectural division of processing by theprocessor and data storage by the memory has proven successful fornearly the entire history of such systems.

For example, a typical general-purpose computer usually includes acentral processing unit (CPU) and a main memory that communicate withone another over one or more communication channels (e.g., data, commandand address buses). Typically, the CPU provides facilities to performvarious arithmetic and logical operations, to provide operationalsequencing, and to otherwise control aspects of the general-purposecomputer. For example, virtually all CPUs provide functions oroperations for reading data from memory, writing data to memory, andexecuting programs comprising a set of instructions that utilizes thedata to perform a predefined task. In addition, CPUs may handleinput/output (I/O) allowing communication with peripherals as well assubsystems outside of the general-purpose computer. CPUs may evenprovide graphics processing to handle generating and updating agraphical display unit (e.g., a monitor), in some examples.

In contrast, the main memory of modem computers, which can include oneor more of static random access memory (SRAM), dynamic random accessmemory (DRAM), read-only memory (ROM), programmable ROM (PROM), flashmemory and a variety of other memory types, typically provides arelatively narrow set of capabilities. Principal among thesecapabilities is storing computer programs and data that are executed andused by the CPU. Among other limited capabilities that may be found inor that are often associated with the main memory of modern computersare certain memory management functions. For example, DRAM memorysubsystems of main memory may possess circuitry for automatic refresh ofdata stored therein.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of examples in accordance with the principles describedherein may be more readily understood with reference to the followingdetailed description taken in conjunction with the accompanyingdrawings, where like reference numerals designate like structuralelements, and in which:

FIG. 1 illustrates a simplified cross sectional view of ametal-insulator phase transition device, according to an example of theprinciples described herein.

FIG. 2 illustrates a plot of a current-voltage (I-V) characteristic of ametal-insulator phase transition device exhibiting current-controllednegative differential resistance, according to an example of theprinciples described herein.

FIG. 3A illustrates a block diagram of a metal-insulator phasetransition (MIT) flip-flop, according to an example of the principlesdescribed herein.

FIG. 3B illustrates a block diagram of a metal-insulator phasetransition (MIT) flip-flop, according to another example of theprinciples described herein.

FIG. 4 illustrates a schematic diagram of a metal-insulator phasetransition (MIT) flip-flop, according to an example of the principlesdescribed herein.

FIG. 5 illustrates a block diagram of a shiftable memory that employs ametal-insulator phase transition (MIT) flip-flop, according to anexample of the principles described herein.

FIG. 6 illustrates a flow chart of a method of setting and holding alogic state of a metal-insulator phase transition (MIT) flip-flop,according to an example of the principles described herein.

Certain examples have other features that are one of in addition to andin lieu of the features illustrated in the above-referenced figures.These and other features are detailed below with reference to theabove-referenced figures.

DETAILED DESCRIPTION

Examples in accordance with the principles described herein provide aflip-flop based on a negative differential resistance (NDR) associatedwith a metal-insulator phase transition (MIT). In particular,current-controlled (CC) NDR of an MIT device may provide a pair ofbi-stable operating points or states, according to examples of theprinciples described herein. The CC-NDR-provided operating statebi-stability of the MIT device may be used to store information,according to various examples. In particular, the bi-stable operatingstates may represent logic states that are used to store theinformation. Further, according to some examples, the stored informationmay be subsequently forwarded or communicated to other devices. Storingand subsequent forwarding of information are principal characteristicsof both a flip-flop and more generally, a memory cell. As such, the MITdevice having CC-NDR to provide the bi-stable operating states thatfacilitate storing and forwarding information may be used to realize anMIT flip-flop, according to various examples. MIT flip-flops and MITmemory cells constructed from the MIT flip-flop are broadly applicableto a number of memory architectures including, but not limited to, shiftregisters and shiftable memory systems, for example.

Flip-flops, or related memory cells that share many operationalcharacteristics with flip-flops, are an integral part of most modemcomputers and related processing systems. In particular, for example,flip-flops and memory cells may be found in virtually all CPUs, memoryregisters and cache (e.g., L1, L2, etc.). In addition, some main memory,most notably recently developed so-called ‘shiftable memory,’ may employflip-flops or SRAM memory cells that operate as flip-flops, for example.

According to examples of the principles described herein, the MITflip-flop and the MIT memory cell may provide relatively fast switchingbetween the operating states (i.e., logic states) as well as low powerconsumption, and in some examples very low power consumption, whencompared to other memory technologies. For example, an individualtwo-terminal MIT device employed in either of the MIT flip-flop or theMIT memory cell may have an overall size on the order of less than about50 by 50 nanometers (nm) and may exhibit sub-nanosecond (ns) switchingtimes. In addition, energy consumed by the MIT device to effectswitching of the MIT device may be less than, and in some examples muchless than, about 100 femtojoules, according to some examples. Further,example flip-flops that include the MIT device having CC-NDR may bereadily integrated with conventional integrated circuits (ICs) thatcomprise one or more of group IV, group III-V and group II-VIsemiconductors, according to some examples. For example, the MIT devicemay be fabricated using a back-end or surface-deposition additiveprocess on a surface of a conventional IC. According to some examples,the MIT device-based flip-flops and memory cells described herein may beemployed in conjunction with various complimentary metal-oxidesemiconductor (CMOS) based circuits, memory systems, central processingunits (CPUs), and various application specific ICs (ASICs).

FIG. 1 illustrates a simplified cross sectional view of ametal-insulator phase transition (MIT) device 10, according to anexample of the principles described herein. The MIT device 10, asillustrated, is a two terminal device comprising a layer 12 disposedbetween a first or ‘top’ electrode 14 and a second or ‘bottom’ electrode16. The layer 12 comprises a metal-insulator phase transition (MIT)material. As such, the layer 12 may be referred to as an ‘MIT materiallayer’ 12 or simply an ‘MIT layer’ 12. According to various examples,the first and second electrodes 14, 16 are conductors that facilitateapplying both of a programming signal (e.g., a programming voltage) anda bias signal (e.g., a bias voltage) to the MIT material of the MITmaterial layer 12. The programming signal may be employed to set anoperating state of the MIT device while the bias signal is used tomaintain the operating state, once set, according to various examples.

In some examples, the MIT material layer 12 is a thin film layer havinga thickness on the order of several tens of nanometers. For example, theMIT material of the MIT material layer 12 may have a thickness betweenabout 10 nanometers (nm) to about 100 nm. In another example, the thinfilm MIT material of the MIT material layer 12 may be between about 20nm and about 50 nm thick. In yet other examples, the MIT material of theMIT material layer 12 may be less than about 30 nm in overall thickness.

By definition herein, the MIT material is a material such as, but notlimited to, a transition metal oxide that is capable of undergoing aphase transition from an insulator to a conductor within at least aportion of the material. Herein, a phase transition from an insulator toa conductor is referred to as an ‘insulator-to-metal phase transition.’In some examples, the insulator-to-metal phase transition may resultfrom or be due to Joule heating of the material that induces filamentarymetallic phase formation, for example. Formation of the filamentarymetallic phase may facilitate conduction of an electric current throughwhat was otherwise an insulator. As such the metal-insulator phasetransition may be temperature-driven, according to some examples. Jouleheating may be field-induced or current-induced, according to variousexamples. A device comprising such a metal-insulator phase transitionmaterial (e.g., a transition metal oxide) may have or exhibit theaforementioned CC-NOR over at least a portion of a current-voltage (I-V)characteristic of the device, for example.

According to various examples, the MIT material of the MIT device 10 maybe substantially any metal oxide or similar material that exhibits or iscapable of exhibiting a current-controlled NOR associated with themetal-insulator phase transition. In particular, the MIT material of theMIT material layer 12 may comprise substantially any transition metaloxide that provides CC-NOR associated with a metal-insulator phasetransition in at least a portion of the MIT material layer 12, accordingto some examples. For example, the MIT material may comprise an oxide ofniobium. In another example, a titanium oxide may be used as the MITmaterial of MIT material layer 12. In other examples, oxides oftungsten, manganese, iron and vanadium as well as doped alloys thereofthat may undergo an MIT transition may be employed as the MIT materialof MIT material layer 12. Other metal oxides that may be employedinclude, but are not limited to, nickel oxide, nickel oxide doped withchromium, strontium titanium oxide, strontium titanium oxide doped withchromium, and various combinations of two or more thereof, for example.

In some examples, the MIT material of layer 12 may comprise acrystalline metal oxide. In some of these examples, the crystallineoxide may be mono-crystalline. In other examples, the MIT material oflayer 12 comprises an amorphous metal oxide. In yet other examples, theMIT material of layer 12 comprises either a nanocrystalline oxide or amicrocrystalline metal oxide. By definition herein, a nanocrystallinemetal oxide is a metal oxide that includes or comprises a plurality ofnano-scale crystallites having sizes of about 50 to 100 nm or less,while a microcrystalline oxide may include crystallites having sizes inthe micron range (e.g., greater than about 100 nm), for example.

The first and second electrodes 14, 16 comprise a conductive material orconductor, according to various examples. For example, the firstelectrode 14 and the second electrode 16 may comprise a metal. The metalused for the first and second electrodes 14, 16 may include, but is notlimited to, gold (Au), silver (Ag), copper (Cu), aluminum (Al),palladium (Pd), platinum (Pt), tungsten (W), vanadium (V), tantalum(Ta), and titanium (Ti) as well as alloys thereof, for example.According to various examples, other metals as well as other materialsthat are or may be rendered conductive (e.g., a highly dopedsemiconductors, conductive oxides, conductive nitrides, etc.) may beemployed as the first electrode 14 and the second electrode 16.Moreover, in some examples, the conductive material of the firstelectrode 14 may be different than the conductive material of the secondelectrode 16. In other examples, the first and second electrodes 14, 16comprise the same conductive material.

Additionally, the first and second electrodes 14, 16 may comprise morethan one layer. For example, a layer of titanium may be employed betweena platinum-based electrode and the metal oxide of the MIT material layer12. In some examples, materials used in the electrodes 14, 16 may act asa diffusion barrier. For example, titanium nitride may be employed as adiffusion barrier. In some examples, a conductive material of one orboth of the first and second electrodes 14, 16 may comprise the metal ofa metal-oxide used as the MIT material layer 12. For example, one orboth of the electrodes 14, 16 may comprise titanium when the MITmaterial layer 12 comprises titanium oxide. Similarly, one or both ofthe electrodes 14, 16 may comprise tantalum when the MIT material layer12 comprises tantalum oxide. In yet other examples, a refractorymaterial such as tungsten may be used for situations in which theelectrode(s) 14, 16 may be exposed to very high temperatures (e.g.,during manufacturing), for example.

According to some examples, the MIT device 10 may exhibit CC-NDR atcertain bias levels when operated near or below certain temperatures(e.g., the ‘certain temperatures’ are at or above room temperature) thatare dependent on a material of the MIT device. In particular, variousMIT materials exhibit CC-NDR when cooled below a critical temperature.For example, cooling a titanium oxide-based MIT device to below about155 kelvins (K) (about −118° Celsius) (e.g., by immersing the MIT devicein liquid helium or liquid nitrogen) may produce CC-NDR in the MITdevice 10 over a range of bias levels. Other materials may exhibitCC-NDR at room temperature, or even higher, for example.

Negative differential resistance (NDR) is defined herein as a negativevoltage-current relationship in a device. In particular, NDR ischaracterized by a decrease in voltage across the device as the currentflowing through the device is increased. In contrast, a non-NDR devicesuch as an ‘ohmic’ or conventional resistive device exhibits a positivevoltage-current relationship. Namely, as the voltage across the deviceincreases, current flowing through the device also always increases.Current-controlled NDR is defined herein as NDR that produces acurrent-voltage (I-V) characteristic of the MIT device that is asingle-valued function of current, albeit possibly a multi-valuedfunction of voltage, in an operational range of the MIT device.

FIG. 2 illustrates a plot of a current-voltage (I-V) characteristic of ametal-insulator phase transition device exhibiting current-controllednegative differential resistance, according to an example of theprinciples described herein. The I-V characteristic plotted in FIG. 2 ismeant to be illustrative of generally observed features of a typical I-Vcharacteristic found in various two-terminal MIT devices. Asillustrated, the MIT device I-V characteristic has a generally S-shapedprofile with a region 20 in a middle portion of the S-shaped profilethat represents a current-controlled negative differential resistance(CC-NDR) region of the MIT device I-V characteristic. The CC-NDR region20 divides the I-V characteristic into a first operational region 30located generally below the CC-NDR region 20 and a second operationalregion 40 located generally above the CC-NDR region 20. The firstoperational region 30 is typified by a relatively higher MIT deviceresistance while the second operational region 40 is characterized by arelatively lower MIT device resistance. Hence, the first operationalregion 30 may be referred to as a ‘high resistance’ region 30 of the I-Vcharacteristic and the second operational region 40 may be referred toas a ‘low resistance’ region 40 of the I-V characteristic, for example.Further as illustrated, the I-V characteristic transitions from theCC-NDR region 20 to the second operational region 40 at a first knee 22and further transitions from the CC-NDR region 20 to the firstoperational region 30 at a second knee 24. The first knee 22 correspondsto a first threshold voltage V_(th,1) while the second knee 24corresponds to a second threshold voltage V_(th,2).

According to various examples, the MIT device exhibiting the I-Vcharacteristic illustrated in FIG. 2 may be configured to operate in astable manner either above or below the CC-NDR region 20 (i.e., withineither of the first or the second operational regions 30, 40). Inparticular, if the MIT device is biased by a bias voltage V_(bias) thatis between the first threshold voltage V_(th,1) and the second thresholdvoltage V_(th,2), the MIT device will exhibit hi-stable operation ineither of the two operational regions 30, 40, according to variousexamples. The ability to remain in both of the first region 30 and thesecond region 40 while the voltage across the device is held within therange V_(th,1)<V<V_(th,2) provides the bi-stability of the MIT deviceoperation. As such, the CC-NDR of the MIT device provides a pair ofbi-stable operating states corresponding the bi-stable operation withinthe two operational regions 30, 40 when configured to be held within thevoltage range of V_(th,1)<V<V_(th,2).

Furthermore, operation in a particular one of the pair bi-stableoperating states is selectable using a programming voltage. Theprogramming voltage may be a voltage that is momentarily applied to theMIT device, according to some examples. Specifically, a particular oneof the pair of hi-stable operating states may be selected by applying aprogramming voltage that is either below the first threshold voltageV_(th,1) or above the second threshold voltage V_(th,2), according tovarious examples. Once the programming voltage is removed and the biasvoltage re-established, the MIT device will tend to return to andoperate in the particular bi-stable operating state that was selected bythe applied programming voltage.

For example, if the bias voltage V_(bias) is provided by a voltagesource in series with a bias resistor, the MIT device will be capable ofoperating at a pair of bi-stable operating points determined by theintersection aloud line 50 and the MIT device I-V characteristic, asillustrated. A first stable operating point 52 of the pair may belocated in the first operating region 30 and may represent a first oneof the pair of bi-stable operating states of the MIT device, forexample. Similarly, a second stable operating point 54 of the pair maybe located in the second operating region 40 and may represent a secondone of the pair of bi-stable operating states of the MIT device, forexample. A slope of the load line 50 is related to a resistance of thebias resistor, as illustrated in FIG. 2.

In the example illustrated in FIG. 2, the first bi-stable operatingstate may be selected by applying a programming voltage to the MITdevice that is less than the first threshold voltage V_(th,1).Alternatively, the second bi-stable operating state may be selected byapplying a programming voltage to the MIT device that is greater thanthe second threshold voltage V_(th,2), for the illustrated example. Inparticular, when a programming voltage that is less than the firstthreshold voltage V_(th,1) is applied to the MIT device, an operatingpoint of the MIT device moves to a point on the I-V characteristic thatcorresponds to the applied programming voltage (i.e., moves below thefirst threshold voltage V_(th,1)). Subsequently, when the programmingvoltage is removed and the bias voltage V_(bias) is re-established, theoperating point of the MIT device moves to and settles at the firstoperating point 52. As long as the MIT device biased with the biasvoltage V_(bias), the MIT device will operate at the first operatingpoint 52 in a substantially stable manner (i.e., the first bi-stableoperating state will be maintained).

On the other hand, application of a programming voltage that is greateror above than the second threshold voltage V_(th,2) will result in theoperating point of the MIT device moving to a corresponding point on theI-V characteristic that is above the second threshold voltage V_(th,2).Subsequent removal of the programming voltage and re-establishment ofthe bias voltage V_(bias) will result in the MIT device operating pointsettling at the second operating point 54 illustrated in FIG. 2. The MITdevice will then operate at the second operating point 54 to maintainthe second bi-stable operating state as long as the voltage biasV_(bias) is provided to the MIT device.

In another example (not illustrated), the bias voltage V_(bias), betweenthe first and second threshold voltages V_(th,1), V_(th,2) may beprovided directly by a voltage source (e.g., without the bias resistor).In this example, a corresponding load line (not illustrated) may besubstantially vertical. As described above, the bi-stable operatingstates of the MIT device are represented by a pair of intersectionpoints between the substantially vertical load line and the I-Vcharacteristic of the MIT device within respective ones of the twooperating regions 30, 40. Accordingly, selection and operation in thebi-stable operating states in this example may be substantially similarto the description above involving the bias resistor and load line 50 inFIG. 2, according to various examples.

The cop operating states of the MIT device also may be referred to as‘resistive states’ as they represent distinct and different absoluteresistances of the MIT device. Moreover, since the bi-stable operatingstates of the MIT device produced by the CC-NDR region 20 may beselectively established or programmed, each of the bi-stable operatingstates also may be generally referred to as a ‘selectable resistance,’‘programmable resistance,’ or a ‘selectable/programmable resistancestate’ of the MIT device, by definition herein.

Further, as used herein, the article ‘a’ is intended to have itsordinary meaning in the patent arts, namely ‘one or more’. For example,‘a metal-insulator phase transition (MIT) device’ means one or more MITdevices and as such, ‘the MIT device’ explicitly means ‘the MITdevice(s)’ herein. Also, any reference to ‘top’, ‘bottom’, ‘upper’,‘lower’, ‘up’, ‘down’, ‘front’, ‘back’, ‘left’ or ‘right’ is notintended to be a limitation herein. Moreover, the term ‘about’ whenapplied to a value herein generally means within the tolerance range ofthe equipment used to produce the value, or in some examples, it meansplus or minus 10%, or plus or minus 5%, or plus or minus 1%, unlessotherwise expressly specified. Moreover, examples herein are intended tobe illustrative only and are presented for discussion purposes and notby way of limitation.

FIG. 3A illustrates a block diagram of a metal-insulator phasetransition (MIT) flip-flop 100, according to an example of theprinciples described herein. FIG. 3B illustrates a block diagram of ametal-insulator phase transition (MIT) flip-flop 100, according toanother example of the principles described herein. According to variousexamples, the MIT flip-flop 100 may function in a manner that issubstantially similar to a data or D-type flip-flop (D flip-flop). Inparticular, the MIT flip-flop 100 stores a logic state or a data valueof a signal at a data or input port D of the MIT flip-flop 100. Thelogic state of the input signal may be stored by the MIT flip-flop 100as a bi-stable operating state of an element or elements (i.e., an MITdevice) of the MIT flip-flop 100, for example. In some examples, a logicstate of an output port Q of the MIT flip-flop 100 takes on or is set tocorrespond with the stored logic state of the MIT flip-flop 100. As witha D flip-flop, one or both of the stored logic state and the output portlogic state of the MIT flip-flop 100 may be retained even when the inputsignal is removed or changes logic states. In various examples, the MITflip-flop 100 may be configured to substantially mimic the functionalityof any of several flip-flops including, but not limited to, a clocked Dflip-flop and a master-slave or multiple stage D flip-flop.

In particular, in some examples, the MIT flip-flop 100 may be configuredas a ‘clocked’ flip-flop to store (e.g., as the bi-stable operatingstate of an element) the logic state of the input signal that is presentduring a clock pulse P_(clk) applied to the MIT flip-flop 100. Forexample, if the input signal at the input port D has a first logic stateS₁ (e.g., a logic high) during at least a portion of the clock pulseP_(clk), the logic state of the MIT flip-flop 100 may be set to acorresponding a first logic state M₁ (e.g., one of a logic high or alogic low), for example. After being set, the first logic state M₁ maybe retained as the stored logic state of the MIT flip-flop 100 after theclock pulse P_(clk) terminates. Furthermore, in the absence of the clockpulse P_(clk), the first logic state M₁ may be retained by the MITflip-flop 100 regardless of whether or not the logic state of the inputsignal changes, for example.

In particular, the stored logic state of the MIT flip-flop 100 maychange according to the input signal logic state only during the clockpulse P_(clk), according to some examples. The stored logic state of theMIT flip-flop 100 may be changed if the input signal, during asubsequent clock pulse P_(clk), has a logic state that corresponds toanother logic state of the MIT flip-flop 100. For example, the MITflip-flop 100 that has a logic state set to the first logic state M₁ maybe changed or set to a second logic state M₂ corresponding to a secondlogic state S₂ of the input signal when the input signal has the secondlogic state 57, during the subsequent clock pulse P_(clk). The clockpulse P_(clk) may be provided to the MIT flip-flop 100 at a clock inputport Clk illustrated in FIG. 3A.

As illustrated in FIG. 3A, the MIT flip-flop 100 comprises ametal-insulator phase transition (MIT) device 110 havingcurrent-controlled negative differential resistance (CC-NDR). The MITdevice 110 is configured to provide a pair of bi-stable operating statesof the MIT device, according to various examples. In some examples, thebi-stable operating states are separated from one another on acurrent-voltage (I-V) characteristic of the MIT device 110 by a CC-NDRregion of the I-V characteristic. According to various examples, abi-stable operating state of the pair is capable of being selected by aprograming voltage. Moreover, once the bi-stable operating state isselected, the bi-stable operating state is capable of being maintainedby a bias voltage applied to the MIT device 110, according to variousexamples. As such, the selectable bi-stable operating states may also bereferred to as programmable operating states where the bi-stableoperating state is selected or programmed by the programming voltage andthen maintained by the bias voltage. According to various examples, theselected bi-stable operating state represents a logic state of the MITflip-flop 100.

According to various examples, the MIT device 110 exhibits an S-shapedI-V characteristic (e.g., see FIG. 2) having a first knee (e.g., knee 22in FIG. 2) that is above a CC-NDR region of the I-V characteristic and asecond knee (e.g., knee 24 in FIG. 2) that is below the CC-NDR region.The first knee corresponds to a first threshold voltage V_(th,1) (e.g.,V_(th,1) in FIG. 2) and the second knee corresponds to a secondthreshold voltage V_(th,2) (e.g., V_(th,2) in FIG. 2), respectively, ofthe S-shaped I-V characteristic, according to some examples. In someexamples, a first one of the bi-stable operating states lies within aregion of the I-V characteristic that is below the second knee andbetween the first and second threshold voltages V_(th,1), V_(th,2). Asecond one of the bi-stable operating states lies within a region of theI-V characteristic that is above the first knee and between the firstand second threshold voltages V_(th,1), V_(th,2), in some examples. Insome examples, the first bi-stable operating state (or resistance state)of the MIT device 110 may be selected by a programming voltage that isless than the first threshold voltage V_(th,1). In some examples, aprogramming voltage that is greater than the second threshold V_(th,2)may select the second bi-stable operating state of the MIT device 110.

In some examples, the MIT device 110 is a two-terminal device. Inparticular, the MIT device 110 may have a first terminal 112 and asecond terminal 114, according to some examples. In some examples, thefirst terminal 112 may be configured to receive the programming voltagethat establishes the selectable bi-stable operating state of the MITdevice 110. In addition, the first terminal 112 may be configured toreceive the bias voltage that holds or maintains the selectableresistance state of the MIT device 110. In some examples, the secondterminal 114 may be connected to a ground potential (i.e., to ground).

In some examples, the two-terminal MIT device 110 may be connected tooperate in voltage mode. In voltage mode, the bi-stable operating statesare represented by a pair of voltages or voltage states at a terminal(e.g., the first terminal 112) or across the terminals 112, 114 of theMIT device 110. For example, FIG. 3A illustrates the MIT device 110 as atwo-terminal device connected in voltage mode with the second terminal114 connected to ground. In other examples, a value of an electriccurrent flowing through MIT device 110 (e.g., entering terminal 112 orexiting terminal 114), is determined by the bi-stable operating state ofthe MIT device 110 and represents the stored logic state of the MITflip-flop 100. For example, the MIT device 110 may be connected inseries between other components of the MIT flip-flop 100. In theseexamples, the MIT device 110 is said to be connected to operate incurrent mode. In particular, in current mode the pair of bi-stableoperating states are represented by a pair of current states of theelectric current that flows through the series-connected MIT device 110.FIG. 3B illustrates the MIT device 110 as a two-terminal deviceconnected in series to operate in current mode, for example.

In some examples, the MIT device 110 comprises a first electrode, asecond electrode, and a metal-insulator phase transition (MIT) materialbetween the first and second electrodes. The MIT device 110 may besubstantially similar to the MIT device 10 illustrated in FIG. 1, forexample. In particular, the metal-insulator phase transition materialmay be in contact with the electrodes, in some examples. In otherexamples, another conductive material layer may be inserted between themetal-insulator phase transition material and one or both of theelectrodes. The other conductive material layer may comprise one or bothof a conductor and a semiconductor, according to some examples.

Referring again to the example illustrated in FIGS. 3A and 3B, the MITflip-flop 100 may further comprise a driver 120. The driver 120 isconfigured to provide the programming signal to establish the bi-stableoperating state and to further set the logic state of the MIT flip-flop100. The driver 120 is also configured to provide the bias voltage tomaintain the established selectable resistance and to hold the logicstate of the MIT flip-flop 100.

In some examples (e.g., as illustrated in FIGS. 3A and 3B), the driver120 comprises a multiplexer 120 having a plurality of inputs. Themultiplexer 120 is configured to select between a data input D of theMIT flip-flop 100 and the bias voltage V_(bias) connected to separateones of the plurality of inputs. The data input may provide a voltagecomprising the programing voltage, according to various examples. Insome examples, the multiplexer 120 may be a logic circuit that acts toselect between the data input D and a voltage source that provides thebias voltage V_(bias). In some examples, the multiplexer 120 orequivalently the driver 120 comprises a switch and a bias resistor (notillustrated in FIGS. 3A and 3B). In some examples, the switch isconfigured to provide the programming voltage (e.g., as a voltagesignal) present at an input port D of the MIT flip-flop 100 to the MITdevice 110 when the switch is ON. In some examples, the bias resistor isconfigured to provide the bias voltage to the MIT device 110 when theswitch is OFF.

For example, the switch may be configured in a first switch position(e.g., ON) to provide a connection between the input port D of the MITflip-flop 100 and the MIT device 110. When the switch is in the firstposition (ON), the voltage signal from the input port D may becommunicated to the first terminal 112 of the MIT device 110 through theswitch, for example. In some examples, the switch may be configured tohave a second switch position when the switch is OFF. The second switchposition may provide a connection between the bias resistor and the MITdevice 110. For example, when the switch is in the second position(OFF), the bias voltage produced at an output of the bias resistor maybe communicated to the first terminal 112 of the MIT device 110.

In some examples, the switch is a single pole, double throw (SPDT)switch having the first switch position (ON) and the second switchposition (OFF). A first circuit formed by the first switch position ofthe SPDT switch forms the connection between the input port D of the MITflip-flop 100 and the MIT device 110 while a second circuit formed bythe second switch position of the SPDT switch connects the bias resistorto the MIT device 100.

In other examples, another type of switch may be used. For example, theswitch may be a single pole single throw (SPST) switch connected betweenthe input port D of the MIT flip-flop 100 and the first terminal 112 ofthe MIT device 110. The bias resistor may also be connected to the firstterminal 112 of the MIT device 110. When the SPST switch is ON (i.e.,the SPST switch is closed), the programming voltage appearing at theinput port D of the MIT flip-flop 100 is communicated to the firstterminal 112 of the MIT device 110. When the SPST switch is OFF (i.e.,the SPST switch is open), the connection to the input port D is brokenand only the bias resistor is connected to the MIT device 110.

In some examples, the MIT flip-flop 100 further comprises an outputdriver 130. The output driver 130 is configured to communicate aselected bi-stable operating state of the MIT device 110 to an outputport Q of the MIT flip-flop 100. For example, the output driver 130 maybe configured to communicate a voltage at the first terminal 112 of theMIT device 110 to the output port Q of the MIT flip-flop 100 (e.g., whenthe MIT device 110 is connected to operate in voltage mode), asillustrated in FIG. 3A. In other examples, the state of the MIT device110 comprises another attribute (e.g., a current or a resistance) andthe output driver 130 communicates the attribute or a representationthereof to the output port Q of the MIT flip-flop 100. In particular,when the MIT device 110 is connected to operate in current mode, asillustrated in FIG. 3B, the output driver 130 may comprise a currentmode driver 130. The current mode driver 130 is a circuit that isconfigured to convert the current state that represents the bi-stableoperating state of the MIT device 110 into a voltage at an output of theMIT flip-flop 100, according to some examples.

For example, the current mode driver 130 may be a current feedback ortransimpedance amplifier comprising an operational amplifier and afeedback resistor R_(f) connected from an output of the operationalamplifier to a negative (e.g., ‘−’) input of the operational amplifier.An input resistance R_(in) of the transimpedance amplifier may beprovided by the MIT device 110, for example. In another example, thecurrent mode driver 130 of FIG. 3B may comprise a current feedbackoperational amplifier.

In some examples, the output driver 130 (e.g., either voltage mode orcurrent mode) may introduce a time delay in the voltage or in anotherattribute that is communicated to the output port Q of the MIT flip-flop100. The time delay may allow for switching between establishing thebi-stable operating state of the MIT device 110 during programming andmaintaining the bi-stable operating state once established, for example.In some examples, the output driver 130 comprises a delay circuit tointroduce the time delay. The delay circuit may include a capacitor,charging and discharging of which provides the delay, for example.

FIG. 4 illustrates a schematic diagram of an MIT flip-flop 100,according to an example of the principles described herein. Inparticular as illustrated, the MIT flip-flop 100 comprises the MITdevice 110 connected between an example of the input driver 120 and anexample of the output driver 130. The input driver 120 illustrated inFIG. 4 comprises a switch 122 and a bias resistor 124. The switch 122 isa complimentary metal-oxide semiconductor (CMOS) 2PDT switch comprisinga p-type metal-oxide-semiconductor (PMOS) transistor 122 a and an n-typemetal-oxide semiconductor (NMOS) transistor 122 b. The PMOS transistor122 a has a source connected to the first terminal 112 of the MIT device110 and a drain connected to the bias resistor 124. The NMOS transistor122 b has a drain connected to the source of the PMOS transistor 122 aand a source connected to the input port D of the MIT flip-flop 100. Agate of the NMOS transistor 122 b is connected to a gate of the PMOStransistor 122 a. In FIG. 4, the MIT device 110 is connected in voltagemode, for example.

As illustrated in FIG. 4, the switch 122 may be turned ON by applicationof a clock pulse P_(clk) for the connected gates of the transistors 122a, 122 b. The clock pulse may be applied by a clock input port Clk ofthe MIT flip-flop 100, for example. In particular, the switch 122 may beON by application of a positive voltage (e.g., the clock pulse) to theconnected gates that turns on the NMOS transistor 122 b and turns offthe PMOS transistor 122 a. For example, the NMOS transistor 122 b may beturned on (e.g., operated in a saturation mode) by an applied voltage atthe connected gates, wherein the applied voltage providesagate-to-source voltage V_(gs) of the NMOS transistor 122 b that exceedsa threshold voltage V_(th) of the NMOS transistor 122 b (e.g.,V_(gs,NMOS)>V_(th,NMOS)). At the same time, the applied voltage thatturns on the NMOS transistor 122 b will ensure that the PMOS transistor122 a is turned off (e.g., operating in pinch-off) since such an appliedvoltage will produce a gate-to-source voltage V_(gs) of the PMOStransistor that is greater than zero volts (V_(gs,PMOS)>0 V). When theNMOS transistor 122 b is turned on, the input port D voltage signal iselectrically connected and communicated through the NMOS transistor 122b to the MIT device 110.

Alternatively, the switch 122 may be turned OFF in the absence of thepositive voltage at the connected gates. In particular, in the absenceof the positive voltage (e.g., the clock pulse), the PMOS transistor 122b is turned on and the NMOS transistor 122 b is turned off For example,the V_(gs) of the NMOS transistor 122 b may be less than or equal tozero voltage (V_(gs,NMOS)≦0 V) to pinch-off the NMOS transistor 122 b inthe absence of the applied positive voltage. At the same time, theabsence of the positive voltage at the connected gates may produce aV_(gs) of the PMOS transistor 122 a that is more negative than athreshold voltage V_(th) of the PMOS transistor 122 a(V_(gs,PMOS)<V_(th)), which places the PMOS transistor 122 a insaturation mode. When the PMOS transistor 122 a is on, the bias resistoris electrically connected to the first terminal 112 of the MIT device110, as illustrated. When electrically connected, the voltage bias t ias provided by the bias resistor is applied to the first terminal 112 ofthe MIT device 110 through the PMOS transistor 122 a. In other examples(not illustrated), another switch circuit instead of the CMOS SPDTswitch 122 illustrated in FIG. 4 may be employed including, but notlimited to, a switch circuit that employs a negative voltage as theclock pulse P_(clk) and a switch circuit that uses complimentary clocksignals (e.g., a CMOS transmission gate).

The bias resistor 124 may be further connected to a bias source toprovide the bias voltage V_(bias) at the MIT device 110. The bias source(not illustrated) may provide a current that produces the bias voltageV_(bias) provided by the bias resistor 124, for example. The biasvoltage and thus a resistance of the bias resistor 124 along with acharacteristics of the bias source are chosen to provide a bias voltageV_(bias) that is between the first and second threshold voltagesV_(th,1), V_(th,2) of the MIT device, according to various examples. Forexample, the bias resistor 124 may have a resistance that is chosen toprovide a load line substantially similar to the load line illustratedin FIG. 2.

FIG. 4 further illustrates the output driver 130 compatible with thevoltage mode connection of the MIT device 110. As illustrated, theoutput driver 130 comprises a plurality of PMOS transistors 132 a and aplurality of NMOS transistors 132 b. The PMOS and NMOS transistors 132a, 132 b of the respective pluralities are connected as a three-stage,inverting CMOS buffer circuit, by way of example and not limitation. Thethree-stage, inverting CMOS buffer circuit inverts a voltage present atthe first terminal 112 of the MIT device 110 and provides sufficientcurrent to drive another device (e.g., another MIT flip-flop), forexample. As illustrated, the output driver 130 further comprises acapacitor 134 between stages of the CMOS buffer circuit. The capacitor134 may have a capacitance of about 4 picofarads (pF), for example. Thecapacitor 134, in conjunction with an impedance of a preceding stage ofthe CMOS buffer circuit, delays propagation of a voltage on the MITdevice 110 to the output port Q of the MIT flip-flop 100.

FIG. 5 illustrates a block diagram of a shiftable memory 200, accordingto an example of the principles described herein. The shiftable memory200 comprises a plurality of memory cells 210 arranged adjacent to oneanother in an array. The memory cells 210 are configured to store one ormore data bits corresponding to a data word. According to variousexamples, a memory cell 210 of the plurality comprises one or more ofthe metal-insulator phase transition (MIT) flip-flops to store the oneor more data bits of the data word. In some examples, the MIT flip-flopof the memory cell 210 is substantially similar to the MIT flip-flop100, described above.

In particular, the MIT flip-flop of the memory cell 210 may comprise anMIT device configured to exhibit a current-controlled negativedifferential resistance (CC-NDR) associated with a metal-insulator phasetransition of the MIT device under electrical (e.g., voltage) bias,according to various examples. In addition, the MIT device of the MITflip-flop is configured to provide a pair of operating states of the MITdevice that are selectable and bi-stable. A particular state of theselectable operating states is capable of being established by aprogramming voltage applied to the MIT device. Once established, theselectable operating state is further capable of being maintained by abias voltage provided to the MIT device. The established selectableoperating state represents a logic state (e.g., symbolized as a logic‘1’ or a logic ‘0’) of the MIT flip-flop and by extension a value of abit or bits stored as a data word by the memory cell 210.

In some examples, the MIT device is substantially similar to the MITdevice 110 described above with respect to the MIT flip-flop 100. Inparticular, in some examples, the MIT device is connected to operate involtage mode while in other examples the MIT device is connected tooperate in current mode. Further, according to some examples, a firstoperating state of the pair of operating states may be selected by afirst programming voltage and a second operating state of the pair maybe selected by a second programming voltage. According to some examples,one or both of the programming voltage and the bias voltage are providedby an input driver. In some examples, the input driver is substantiallysimilar to the driver 120 described above with respect to the MITflip-flop 100.

Further, as illustrated in FIG. 5, the shiftable memory 200 furthercomprises a controller 220 to select and to shift a contiguous subset ofdata words within the array of memory cells. The contiguous subset has alength that is less than a total length of the array. Further, a shiftmay represent one of either an upshift or a downshift and includes onlythe contiguous subset of data words within the array selected by thecontroller 220.

According to various examples, the shiftable memory 200 providesshifting of the contiguous subset of data words stored in the shiftablememory 200. Further, shifting of data words by the shiftable memory 200shifts only the data words in the contiguous subset and not other storeddata words. In particular, when the shiftable memory 200 performs ashift of the contiguous subset, the shift does not shift other storeddata words located outside of the contiguous subset. Further, the shiftmoves the contiguous subset of stored data words without changing orotherwise affecting an order of the stored data words in the contiguoussubset, according to some examples. The shift provided by the shiftablememory 200 may be used to one or both of insert new data words into theshiftable memory 200 and delete data words stored therein, for example.

An external resource (e.g., a processor 230) may communicate data to andfrom the shiftable memory 200 via a data bus (Data I/O) 234, accordingto some examples. An address and a length of the contiguous subset maybe communicated to the shiftable memory 200 using an address bus(Address) 232, for example. An address bus that carries both the addressand the length or alternatively a pair of addresses may be employed,according to various examples.

FIG. 6 illustrates a flow chart of a method 300 of setting and holding alogic state of a metal-insulator phase transition (MIT) flip-flop,according to an example of the principles described herein. The method300 of setting and holding a logic state in an MIT flip-flop comprisesapplying 310 a programming voltage to a metal-insulator phase transition(MIT) device of the MIT flip-flop. The applied programming voltage isconfigured to select between a pair of bi-stable operating states of theMIT device that represent logic states of the MIT flip-flop. Accordingto various examples, the MIT device has a current-controlled negativedifferential resistance (CC-NDR) and is configured to provide thebi-stable operating states of the MIT device.

In particular, according to some examples, the programming voltage isconfigured to set the logic state of the MIT flip-flop by selecting orequivalently programming the bi-stable operating state of the MITdevice. In some examples, when the applied 310 programming voltage isbelow a first threshold V_(th,1), a first bi-stable operating state ofthe pair is selected. Alternatively, when the applied 310 programmingvoltage is above a second threshold V_(th,2), a second bi-stableoperating state is selected, in some examples. In some examples, thefirst threshold V_(th,1) is substantially similar to the first thresholdV_(th,1) illustrated in FIG. 2. The second threshold V_(th,2) may besubstantially similar to the second threshold V_(th,2) illustrated inFIG. 2, according to some examples. In some examples, the MIT flip-flopand the MIT device are substantially similar to the MIT flip-flop 100and MIT device 110 described above.

Further, as illustrated in FIG. 6, the method 300 of setting and holdinga logic state of an MIT flip-flop further comprises providing 320 a biasvoltage to the MIT device to hold the MIT flip-flop logic state. Thebias voltage holds the selected bi-stable operating state in the absenceof the programming voltage, for example.

In some examples (not illustrated), the method 300 of setting andholding a logic state of an MIT flip-flop further comprises providingthe programming voltage during a first time period to be applied 310 tothe MIT device from an input port of the MIT flip-flop. The first timeperiod corresponds to a time period when the programming voltage isbeing applied 310. A switch connected between the input port and the MITdevice, for example, may provide the programming voltage. In anotherexample, the programming voltage may be provided by a multiplexer.

In some examples (not illustrated), the method 300 of setting andholding a logic state of an MIT flip-flop further comprisescommunicating a signal representing a selected bi-stable operating stateof the MIT device to an output port of the MIT flip-flop. Thecommunicated signal may represent the logic state of the MIT flip-flop,for example. In some examples, the signal may represent a voltage of theMIT device (e.g., when operated in voltage mode). In other examples, thesignal may represent a current flowing through the MIT device (e.g.,when operated in current mode). The signal may be communicated using anoutput driver, for example. The output driver may be substantiallysimilar to the output driver 130 described above. In particular, theoutput driver may comprise a time delay circuit (e.g., a capacitivedelay) to delay communication of the voltage, according to someexamples.

Thus, there have been described examples of a metal-insulator phasetransition flip-flop and a method of setting and holding a logic stateof a metal-insulator phase transition flip-flop that employ ametal-insulator phase transition having CC-NDR to store data. It shouldbe understood that the above-described examples are merely illustrativeof some of the many specific examples that represent the principlesdescribed herein. Clearly, those skilled in the art can readily devisenumerous other arrangements without departing from the scope as definedby the following claims.

What is claimed is:
 1. A metal-insulator phase transition (MIT)flip-flop comprising: a metal-insulator phase transition (MIT) devicehaving current-controlled negative differential resistance (CC-NDR) toprovide a pair of bi-stable operating states, the bi-stable operatingstates being separated from one another on a current-voltage (I-V)characteristic of the MIT device by a CC-NDR region of the I-Vcharacteristic, wherein a bi-stable operating state of the pair iscapable of being selected by a programing voltage, and wherein once thebi-stable operating state is selected, the bi-stable operating state iscapable of being maintained by a bias voltage applied to the MIT device,the selected bi-stable operating state representing a logic state of theMIT flip-flop.
 2. The metal-insulator phase transition (MIT) flip-flopof claim 1, further comprising a multiplexer to select between a datainput of the MIT flip-flop and a bias voltage source, the data inputproviding a voltage comprising the programing voltage.
 3. Themetal-insulator phase transition (MIT) flip-flop of claim 2, wherein themultiplexer comprises a switch and a bias resistor, the switch toconnect the MIT device to the data input when the switch is ON, the biasresistor to provide the bias voltage to the MIT device when the switchis OFF.
 4. The metal-insulator phase transition (MIT) flip-flop of claim1, wherein the MIT device is connected to operate in a voltage mode, thepair of bi-stable operating states being represented by a pair ofvoltage states at a terminal of the MIT device.
 5. The metal-insulatorphase transition (MIT) flip-flop of claim 4, further comprising anoutput driver to communicate a voltage state at the MIT device terminalto an output of the MIT flip-flop, the output driver having a delaycircuit to introduce a time delay in communicating the voltage state. 6.The metal-insulator phase transition (MIT) flip-flop of claim 1, whereinthe MIT device is connected in series to operate in current mode, thepair of bi-stable operating states being represented by a pair ofcurrent states of an electric current that flows through theseries-connected MIT device.
 7. The metal-insulator phase transition(MIT) flip-flop of claim 6, further comprising a current mode driver toconvert a current state of the pair of current states into a voltage atan output of the MIT flip-flop.
 8. The metal-insulator phase transition(MIT) flip-flop of claim 1, wherein the MIT device comprises: a firstelectrode; a second electrode; and a metal-insulator phase transitionmaterial between the first electrode and the second electrode, whereinthe first electrode and the second electrode serve as terminals of theMIT device.
 9. The metal-insulator phase transition (MIT) flip-flop ofclaim 8, wherein the metal-insulator phase transition material comprisesan oxide of one of niobium, titanium and vanadium to undergo themetal-insulator phase transition, and wherein one or both of the firstelectrode and the second electrode comprise one or more of gold, silver,platinum, tungsten, copper, titanium, tantalum.
 10. A metal-insulatorphase transition (MIT) flip-flop comprising: a first electrode and asecond electrode; a metal-insulator transition (MIT) material connectedbetween the first and second electrodes and having current-controllednegative differential resistance (CC-NDR) when under electrical bias,the MIT material between the electrodes to exhibit a pair of operatingstates of the MIT flip-flop that are bi-stable; and an input driver toselect one of the operating states in response to a programming voltageand to provide a bias voltage to maintain the selected operating state,a first operating state of the pair being selected by a firstprogramming voltage and a second operating state of the pair beingselected by a second programming voltage, wherein the selected operatingstate represents a logic state of the MIT flip-flop.
 11. Themetal-insulator phase transition (MIT) flip-flop of claim 10, whereinthe input driver comprises a multiplexer to select between a data inputof the MIT flip-flop and the bias voltage, the data input comprising oneof the first programming voltage and the second programming voltage. 12.The metal-insulator phase transition (MIT) flip-flop of claim 10,further comprising an output driver to communicate the selectedoperating state to an output of the MIT flip-flop, the output drivercommunicating an indication of a voltage at the first electrode when thefirst and second electrodes and the MIT material are connected forvoltage mode operation, the output driver communicating an indication ofa current flowing between the first and second electrodes and throughthe MIT material when the first and second electrodes and MIT materialare connected for current mode operation.
 13. A shiftable memoryemploying the metal-insulator phase transition (MIT) flip-flop of claim10, the shiftable memory comprising: a plurality of memory cellsarranged adjacent to one another in an array, a memory cell of theplurality to store one or more data bits corresponding to a data word,the memory cell comprising one or more of the MIT flip-flops to storethe one or more data bits of the data word; and a controller to selectand to shift a contiguous subset of data words within the array, thecontiguous subset having a length that is less than a total length ofthe array, a shift representing either an upshift or a downshift of onlythe contiguous subset of data words within the array selected by thecontroller.
 14. A method of setting and holding a logic state of ametal-insulator phase transition (MIT) flip-flop, the method comprising:applying a programming voltage to a metal-insulator phase transition(MIT) device to select between a pair of bi-stable operating states ofthe MIT device that represent logic states of the MIT flip-flop, the MITdevice having a current-controlled negative differential resistance(CC-NDR) that provides the pair of bi-stable operating states; andproviding a bias voltage to the MIT device to hold the selectedbi-stable operating state in the absence of the programming voltage,wherein the programming voltage being below a first threshold selects afirst bi-stable operating state of the pair, and wherein the programmingvoltage being above a second threshold selects a second bi-stableoperating state of the pair.
 15. The method of setting and holding alogic state of an MIT flip-flop of claim 14, further comprising:providing the programming voltage to the MIT device from an input portof the MIT flip-flop during a first time period, the first time periodcorresponding to a time period when the programming voltage is applied;and communicating a signal representing the selected bi-stable operatingstate of the MIT device to an output port of the MIT flip-flop, whereinthe communicated signal is the logic state of the MIT flip-flop.